Non-volatile memory cells use the oxide grown on the crystalline silicon substrate as their Fowler-Nordheim tunnel oxide. Electrons tunnel through this oxide into the floating gate where they stay until they are pulled out. This tunnel oxide has a barrier height of 3.2 eV. In order to induce electron tunneling through this barrier height, a relatively high voltage across the tunnel oxide is required. For example, for a 100 .ANG. tunnel oxide, more than 10 volts is required across the tunnel oxide in a typical flash memory application. On the other hand, the barrier height of the oxide grown on an amorphous silicon layer in accordance with the present invention is in the range of about 1.6 to about 2.0 eV, and in one embodiment only about 1.8 eV. Because of this lower barrier height, the electric field strength required to induce the same Fowler-Nordheim tunnel current is smaller. This is useful for low voltage applications.
U.S. Pat. 4,642,881 discloses a method of manufacturing a non-volatile semiconductor memory device having a gate oxide layer including a relatively thin silicon dioxide layer. This gate oxide layer including the thin silicon dioxide layer is formed by the steps of forming the gate oxide film on a semiconductor element region in a silicon substrate; removing a portion of the gate oxide film to expose a portion of the silicon substrate; implanting impurity ions in the exposed portion of the substrate to an extent that a peak concentration of the impurity ions exceeds a solid solution limit at a temperature of the following thermal annealing step; activating the implanted impurity by thermal annealing so as to form a high impurity concentration layer and thermally oxidizing a surface of the high impurity concentration layer to form the thin silicon dioxide layer.